1. Field of the Invention
The present invention relates to a device interface and, more specifically, to systems and methods for improved matching of interfaces with data flow.
2. State of the Art
Interfaces provide access points for exchanging data within electronic or computer systems. An example of an interface includes the access points associated with, for example, a memory device. Generally, a memory device includes a specific number of pins that are dedicated or at least shared for accessing and storing information within memory locations of a memory device. To minimize the number of dedicated pins for an interface, access points that function both as data inputs and outputs have been developed. FIG. 1 illustrates a pair of devices coupled together according to a shared interface. While electronic devices may incorporate various form factors, the present illustration is drawn to data storage and, more particularly, memory devices. An interface system 10 includes a memory controller 12 coupled to a memory device 14 according to a bidirectional interface 16. Bidirectional interface 16 combines both the “D” inputs and “Q” outputs of memory device 14 into shared pins to reduce the overall interface pin count, X.
While the pin count of a memory device may be reduced through the use of a bidirectional interface, such a functionally shared interface creates a throughput-bottleneck when, for example, a memory controller and memory device are capable of generating memory access commands for reading and writing to a memory device that is capable of responding thereto in a generally simultaneous manner.
In response to increased memory bandwidth demands, separate input and output interfaces have been proposed and implemented. FIG. 2 illustrates an interface system 20 including a memory controller 22 coupled to a memory device 24 according to a separate symmetric interface 26. Separate symmetric interface 26 includes a symmetric read data interface 28 and a symmetric write data interface 30. Each of the interfaces, symmetric read data interface 28 and symmetric write data interface 30, include an equivalent number of pins, X for interfacing with memory device 24. Separating the read and write data interfaces provides improved performance including signal integrity, no bus turn-around time, reduced I/O capacitance, etc. However, doubling of interface pins resulting from separating the read and write data interfaces creates an increased interface dimension for memory device 24, which increases the overall area required for integrating memory device 24 into an electronic system. Therefore, there is a need to provide an improved device interface while reducing the overall affect to the form factor of the device and overall system.